Time to take Moore’s Law into our own hands

Moore’s law; the premise that transistor density will double every 24 months, has long been the guiding principle of the semi industry. For a couple of decades, notably the nineties and the oughts, this directly resulted in performance doubling, but there has to be a limit to how small the transistors can get before they can no longer keep the electrons in line.

Transistor size has decreased rapidly over the last few decades (there’s even a clever animation for those who want to see it in motion), though shrinking the process nodes isn’t always profitable. When a fabrication plants costs $10B the return on investment is hard to find –so the limits might be more financial than technical. A 7nm process requires $200M capital investment per 1k monthly production, double that of 28nm. If we start talking about 5, or even 3nm, then the costs escalate.

Not that it’s clear what process node everyone is using these days – a 7nm “process” results in gates that are 20nm long, and TSMC’s 7nm is equivalent to Intel’s 10nm. If we’re going to compare then we really need to see the transistor density per square millimeter, or perhaps we should say cubic millimeter.

Adding a third dimension can increase the transistor count without using smaller transistors. TSMC’s VP of research reckons that his company can sustain the increasing transistor count for “decades” by using stacked-chip designs.

Intel has certainly been pushing in this direction, showing its LakeField processor – a 3D stacked package including a mix of processor cores, I/O dies and memory die. Intel is also using its 3D packaging to enable its latest gen 10nm FPGAs. Other vendors are using a mix of processing die and stacks of HBM memory die to bypass transistor density constraints – packing often referred to as 2.5D.

Packaging can also reduce the risk of using low process nodes. Restricting the highest-cost process to the most-critical parts of a chip can reduce the overall costs, and increase product volume. AMD has been usefully combining process notes for its Zen based Ryzen and Epyc processors, and its most recent Zen2 based designs mixes 7nm and 14nm die on a 2D package.

Moore’s law only mentions increasing the number of transistors, in a two-dimensional space. Expanding that to three dimensions is an easy way to increase the count without squeezing the transistor size any further. Not that we couldn’t – it seems clear that 5nm, and even 3nm, are technically possible, but the more-important question is if such innovation will be profitable. Reducing the process node has worked well in the past, but (as we often say at Gartner) companies need to look beyond what they did last year, if they want to be certain of still being in business next year.

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Bill Ray
Sr Director Analyst, Semiconductors & Electronics I
3 years at Gartner
32 years IT Industry

Bill Ray provides written research and inquiry support covering wireless connectivity, primarily for Product Managers and Tech CEOs. His researches focus on evolving standards for IoT connectivity and 5G services, and the semiconductors needed to support them.Read Full Bio